module uart_tx_control(
    input            clk, 
    input            rst_n,

    output reg [7:0] uart_data,
    output reg       data_en,
    input            uart_tx_end
);
//parameter define
parameter DELAY_10MS = 500000;
reg [31:0] cnt_10ms;
wire delay_10ms_done;
//data define
reg [31:0] cnt_1s;
//cnt_10ms
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt_10ms <= 'd0;
    end
    else if (cnt_1s == DELAY_10MS-1 && uart_tx_end) begin
        cnt_10ms <= 'd0;
    end
    else begin
        cnt_10ms <= cnt_10ms + 1;
    end
end
//data_en
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        data_en <= 1'b0;
    end
    else if (delay_10ms_done) begin
        data_en <= 1'b1;
    end
    else if (uart_tx_end) begin
        data_en
    end
end
//cnt_1s
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt_1s <= 'd0;
    end
    else if (cnt_1s == 49999999) begin
        cnt_1s <= 'd0;
    end
    else begin
        cnt_1s <= cnt_1s + 1;
    end
end
//uart_data
always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        uart_data <= 'd0;
    end
    else if (uart_data >= 10) begin
        uart_data <= 'd0;
    end
    else if (cnt_1s == 499999999) begin
        uart_data <= uart_data + 1;
    end
end
endmodule //uart_tx_control